Nonvolatile semiconductor memory device and process for producing the same

ABSTRACT

The present invention is envisioned to realize miniaturization, low voltage operation and high reliability of a nonvolatile semiconductor memory device, and simplification of its production process. Interpoly dielectric film  109   a  of the nonvolatile semiconductor memory device is composed of a nitrogen-introduced CVD SiO 2  film, and is used as gate oxide film of MOS transistors in the low voltage region of the peripheral circuit region. Gate oxide film of MOS transistors in the high voltage region of the peripheral circuit region is composed of a laminate of said SiO 2  film  109   a  and a nitrogen-introduced CVD SiO 2  film. According to the present invention, reliability of gate oxide film of peripheral circuit MOS transistors of the nonvolatile semiconductor memory device and its transistor characteristics are improved. It is also possible to realize miniaturization and low voltage operation of the nonvolatile semiconductor memory device. Further, simplification of its production process is made possible.

FIELD OF THE INVENTION

[0001] The present invention relates to a nonvolatile semiconductormemory device and a process for producing the device, and itspecifically pertains to the techniques for realizing miniaturization,low voltage operation, high reliability and simplified productionprocess of the device.

BACKGROUND OF THE INVENTION

[0002] Flash memory, which is a typical example of nonvolatilesemiconductor memory device, is rapidly expanding its market as a memoryunit for small-sized portable information devices such as cellularphones, digital still cameras, etc., as it is handy to carry,shock-proof and also capable of electrical bulk erasing on board.

[0003] This flash memory, as for instance illustrated in FIG. 18,usually consists of memory cells M which store data and MOS field effecttransistors P constituting peripheral circuits for selecting theprogramming/erasing or read bits or generating a necessary voltage inthe chips.

[0004] Unitary memory cell M comprises a set of MOS field effecttransistors each consisting of a silicon (Si) substrate 201 havingsource and drain diffusion layers (not shown), a P well 204 a formed onsaid Si substrate, a floating gate 207 and a control gate 209 both ofwhich comprise mainly a polycrystalline Si film, an interpoly dielectricfilm 208 separating said gates 207 and 209, and a tunnel dielectric film206 separating said floating gate 207 and P well 204 a, and a pluralityof such memory units are arranged as a matrix. As the interpolydielectric film separating the floating and control gates of each memorycell, there is usually used a so-called ONO film which is a stacked filmcomprising a silicon nitride (Si3N4) film sandwiched between the SiO₂films, said ONO film being higher in permittivity and smaller in leakagecurrent than the SiO₂ film.

[0005] Peripheral circuit P consists of a combination of MOS fieldeffect transistors each comprising a P well 204 b and an N well 205formed in an Si substrate 201, source and drain diffusion layers 212 aand 212 b, and a gate electrode 211 mainly comprising a polycrystallineSi film formed on the well with the interposition of a gate insulatingfilm 210. Gate insulating film 210 usually comprises a SiO₂ film formedby thermal oxidation method.

[0006] Each unitary memory cell M and peripheral circuit transistors Pare usually separated by an isolation region 202 comprising a thickoxide film. The quantity of charge accumulated in the floating gate iscontrolled by biasing the positive or negative voltage generated by theperipheral circuit to the control gate 209, and the threshold voltage ofthe memory cell transistors is varied accordingly to therebydiscriminate “0” and “1” of data.

[0007] However, increase of density of said nonvolatile semiconductormemory device has given rise to the new problems over the MOStransistors P for peripheral circuits and the memory cells M.

[0008] One of such problems is deterioration of characteristics andreliability of the MOS transistors for peripheral circuits due todegradation of the gate oxide film.

[0009] In flash memory, a high voltage, such as, for example, 18 V, isapplied to the word line at writing/erasing. For the MOS transistors forperipheral circuits exposed to such high voltage, the gate oxide filmthickness is increased to, for instance, around 25 nm so that the filmcan withstand such high voltage. However, in case the shallow grooveisolation method is applied in place of the conventional selectiveoxidation method (LOCOS) for isolation between the peripheral MOStransistors for the purpose of miniaturization of the elements, if thethick (such as 25 nm) gate oxide film is formed by the thermal oxidationmethod, there arises a situation in which the thickness of the gateoxide film adjacent to the shallow groove isolation region becomesexcessively small in comparison with the active region. This gives riseto some serious problems such as “kink” of current-voltagecharacteristics of the MOS transistors and lowering of breakdown voltageof the gate oxide film.

[0010] The second problem is difficulty in thinning of the interpolydielectric film of the memory cells M which is essential for thereduction of programming voltage.

[0011] The voltage Vfg applied to the floating gate for theprogramming/erasing operation of the flash memory is given by thefollowing equation:

Vfg=C2·Vcg/(C1+C2)  (1)

[0012] wherein Vcg is voltage applied to the control gate, and C1 and C2are capacitance of the tunnel dielectric film and the interpolydielectric film, respectively. In order to transfer the voltage appliedto the control gate efficiently to the floating gate to reduce theprogramming voltage, it is effective to increase C2, namely to makethinner the interpoly dielectric film. However, in the case of the “ONOfilm”, i.e. a stacked film comprising a silicon nitride (Si3N4) filmsandwiched between the SiO₂ films, which has been widely used in theart, if the thickness of the SiO₂ film on each side of the laminate ismade 5 nm or less, there would arise the problem that the chargeaccumulated in the floating gate might leak out to the control gate,that is, actualization of so-called retention degradation. Also, whenthe SiO₂ film on the upper side of the laminate is made 5 nm inthickness, it is necessary to deposit the Si3N4 film to a thickness ofaround 10 nm or greater for preventing oxidation of the polycrystallineSi layer on the lower side. Thus, the limit of possible reduction ofthickness of the ONO film was around 15 nm in terms of effective oxidethickness.

[0013] JP-A-10-242310 discloses a technique for reducing the programmingvoltage by lessening the film thickness by applying anitrogen-introduced single-layer CVD SiO₂ film as the interpolydielectric film in place of the conventional ONO film.

[0014] However, when the gate oxide film of the peripheral circuit MOStransistors was formed by the thermal oxidation method after forming theinterpoly dielectric film, as commonly practiced in manufacture of theconventional flash memories, there would arise the problem that thehighly doped floating gate polycrystalline Si be oxidized thicklybecause the single-layer CVD SiO₂ film has no oxidation resistanceunlike the ONO film. Therefore, development of a reliable method forforming a gate oxide film of the peripheral circuit MOS transistors whenusing a single-layer CVD SiO₂ film as the interpoly dielectric film formemory cell was essential.

[0015] The third problem is the increase of the number of the steps inthe production process.

[0016] In the conventional flash memory production process, the tunneldielectric film 206 of memory cells, their interpoly dielectric film 208and the gate insulating film 210 of peripheral circuit MOS transistorshave been formed severally in succession, so that the process involvedmany steps and this has been an obstacle to the effort for costreduction. Recently, an idea of the techniques for making two typethickness of the gate oxide film of MOS transistors in the peripheralcircuit region is proposed for attaining further enhancement ofprogramming/erasing speed and read speed of the flash memory. It isconsidered that the simplification of the flash memory productionprocess will become an important subject for study in the art.

[0017] The above-said three problems are closely associated with eachother from the viewpoint of formation of interpoly dielectric films ofmemory cells and gate oxide film of peripheral circuit MOS transistors,and for the solution of these problems, the development of a novelnonvolatile semiconductor memory device and its production process hasbeen required.

[0018] Accordingly, an object of the present invention is to make highlyreliable the gate oxide film of peripheral circuit MOS transistors ofnonvolatile semiconductor memory device and to improve its transistorcharacteristics.

[0019] Another object of the present invention is to provide a processfor forming the interpoly dielectric film and the gate oxide film of MOStransistors in the peripheral circuit region that accord with theminiaturization and low-voltage operation of nonvolatile semiconductormemory device.

[0020] Still another object of the present invention is to simplify theproduction process of nonvolatile semiconductor memory device.

SUMMARY OF THE INVENTION

[0021] In the nonvolatile semiconductor memory device of the presentinvention, in order to solve the first problem mentioned above, the gateinsulating film of MOS field effect transistors composing the peripheralcircuit is formed by an insulating film, for example, a CVD SiO₂ film,deposited on a semiconductor substrate. This can eliminate thinning ofthe thickness of the gate oxide film at the part adjoining to theshallow groove isolation region even when using the shallow grooveisolation method for the isolation between the MOS field effecttransistors, making it possible to prevent “kink” of the MOS fieldeffect transistor characteristics. This also allows avoidance oflowering of breakdown voltage of the gate oxide film. It is noticeablethat in case the peripheral circuit is constituted by MOS field effecttransistors having two or more different gauges of gate insulating filmthickness, an especially significant effect is produced when theabove-said insulating film is applied to the high voltage MOS fieldeffect transistors with a greater gate insulating film thickness.

[0022] Also, by using a stacked film (e. g. CVD SiO₂ film) comprising aninsulating film formed by thermally oxidizing the semiconductorsubstrate surface and another insulating film deposited on thefirst-said insulating film as the gate insulating film of MOS fieldeffect transistors of peripheral circuit, it is possible to compensatethe thickness of the gate oxide film at the part adjacent to the shallowgroove isolation region with the deposited insulating film, so that asin the above-said case using a single-layer deposited insulating film,it becomes possible to prevent kink of the MOS field effect transistorcharacteristics and to avoid lowering of breakdown voltage of the gateoxide film. In this case, it is preferable for producing the desiredeffect to make the thickness of the deposited insulating film greaterthan that of the insulating film formed by thermal oxidation.

[0023] In order to solve the above-said second problem, in thenonvolatile semiconductor memory device production process of thepresent invention, the gate insulating film of MOS field effecttransistors constituting the peripheral circuit is formed by aninsulating film, for example, CVD SiO₂ film, deposited on asemiconductor substrate. By this measure, even when a CVD SiO₂ film isused as the interpoly dielectric film and the gate insulating film isformed after forming the interpoly dielectric film, it is possible toprevent the said interpoly dielectric film (CVD SiO₂ film) from beingoxidized thickly.

[0024] In case the whole or part of the gate insulating films ofperipheral circuit are made of a film formed by thermal oxidation, it ispossible to prevent abnormal oxidization of the interpoly dielectricfilm, or CVD SiO₂ film, by finishing the step of thermal oxidation ofthe semiconductor substrate surface prior to the step of forming theinterpoly dielectric film.

[0025] For solving the above-said third problem, in the nonvolatilesemiconductor memory device and its production process according to thepresent invention, the insulating film (for example, CVD insulatingfilm) deposited for forming the interpoly dielectric film is used as thewhole or part of the gate insulating films of MOS field effecttransistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is schematic sectional illustrations (1) of Example 1 ofthe present invention.

[0027]FIG. 2 is schematic sectional illustrations (2) of Example 1 ofthe present invention.

[0028]FIG. 3 is a graph showing the relation between gate voltage andgate current.

[0029]FIG. 4 is a graph showing distribution of breakdown voltage of thegate oxide film.

[0030]FIG. 5 shows geometries of the gate oxide film in the vicinity ofthe shallow groove isolation region.

[0031]FIG. 6 is the graphs showing distribution of nitrogenconcentration in the SiO₂ film.

[0032]FIG. 7 is schematic sectional illustrations (1) of Example 2 ofthe present invention.

[0033]FIG. 8 is schematic sectional illustrations (2) of Example 2 ofthe present invention.

[0034]FIG. 9 is schematic sectional illustrations (3) of Example 2 ofthe present invention.

[0035]FIG. 10 is schematic sectional illustrations (1) of Example 3 ofthe present invention.

[0036]FIG. 11 is schematic sectional illustrations (2) of Example 3 ofthe present invention.

[0037]FIG. 12 is schematic sectional illustrations (3) of Example 3 ofthe present invention.

[0038]FIG. 13 is schematic sectional illustrations of Example 4 of thepresent invention.

[0039]FIG. 14 is schematic sectional illustrations (1) of Example 5 ofthe present invention.

[0040] FIOG. 15 is schematic sectional illustrations (2) of Example 5 ofthe present invention.

[0041]FIG. 16 is schematic sectional illustrations (1) of Example 6 ofthe present invention.

[0042]FIG. 17 is schematic sectional illustrations (2) of Example 6 ofthe present invention.

[0043]FIG. 18 is a schematic sectional illustration of the prior art.

(DESCRIPTION OF REFERENCE NUMERALS)

[0044]101: Si substrate; 102: shallow groove isolation region; 103: wellisolation region; 104 a, 104 b, 104 c: P wells; 105 a, 105 b: N wells;106: thermal oxide film; 107, 107 a, 107 b, 107 c, 107 d, 107 e, 107 f:phosphorus-doped polycrystalline Si film; 108, 108 a, 109, 109 a:nitrogen-introduced SiO₂ film; 110, 110 a, 110 b: phosphorus-dopedpolycrystalline Si film; 111 a, 111 b, 111 c: N source/drain region; 112a, 112 b: P source/drain region; 113: thermal oxide film; 114, 114 a:phosphorus-doped polycrystalline Si film; 115, 115 a: SiO₂ film; 116:source/drain region; 117: photoresist; 118, 118 a, 118 b, 118 c, 18 d,118 e: phosphorus-doped polycrystalline Si film; 119, 119 a: SiO₂ film;120, 120 a, 120 b: phosphorus-doped polycrystalline Si film; 121: SiO₂film; 122: Si3N4 film; 123, 123 a: thermal oxide film; 124, 124 a:thermal oxide film; 125, 125 a: nitrogen-introduced SiO₂ film; 126, 126a: thermal oxide film; 200: gate oxide film; 201: Si substrate; 202:oxide film for isolation; 203: well isolation region; 204 a, 204 b: Pwells; 205: N well; 206: thermal oxide film; 207: phosphorus-dopedpolycrystalline Si film; 208: ONO interpoly dielectric film; 209:phosphorus-doped polycrystalline Si film; 210: thermal oxide film; 211:phosphorus-doped polycrystalline Si film; 212 a, 212 b: source/drainregion; M: memory cell; P, P′: MOS transistors.

DETAILED DESCRIPTION OF THE INVENTION EXAMPLE 1

[0045] In this example, a nitrogen-introduced CVD SiO₂ film was used asthe interpoly dielectric film of memory cells of nonvolatilesemiconductor memory device and as the gate oxide film of peripheralcircuit MOS transistors. By forming these films simultaneously, it wastried to attain improvement of peripheral circuit MOS transistorcharacteristics, miniaturizing of memory cells, reduction of operatingvoltage and simplification of the production process.

[0046] The procedure of producing the nonvolatile semiconductor memorydevice of this Example is shown in FIGS. 1 and 2. This nonvolatilesemiconductor memory device comprises a memory cell region in which aplurality of data-accumulating memory cells are arranged matrix-wise anda peripheral circuit region where a plurality of MOS transistorsconstituting peripheral circuits operative to select programming/erasingand read bits and to generate necessary voltage in the chips aredisposed.

[0047] The peripheral circuit region is divided into a low voltageregion where only a relatively low voltage such as supply voltage of,for example, 3.3V is applied and a high voltage region where a highvoltage, such as 18 V, necessary for programming/erasing is applied. Thelow voltage region and the high voltage region are both comprised of aplurality of NMOS transistors and PMOS transistors formed on the P wells104 b, 104 c and the N wells 105, 105 b, respectively. Memory cells arethe typical flash memories called NOR type, which are formed on thecorresponding P wells 104 a.

[0048]FIGS. 1 and 2 show the sectional views parallel to the word linesof memory cells and perpendicular to the gate lines of peripheralcircuit MOS transistors.

[0049] The production process is described below.

[0050] First, shallow groove isolation regions 102 separating memorycells and peripheral circuit MOS transistors were formed on a p-type Sisubstrate 101 with surface orientation (100) (FIG. 1(a)).

[0051] Then, P well regions 104 a, 104 b, 104 c, N well regions 105 a,105 b and isolation regions 103 were formed by ion implantation method(FIG. 1(b)).

[0052] Next, SiO₂ film 106 functioning as a tunnel dielectric film ofeach memory cell was formed to a thickness of 9 nm by thermal oxidationmethod (FIG. 1(c)).

[0053] This was followed by 150 nm deposition of a phosphorus-dopedpolycrystalline Si film which proves a floating gate (FIG. 1(d)).

[0054] Said polycrystalline Si film 107 was patterned by lithography anddrying etching (polycrystalline Si film 107 becomes 107 a). By thisoperation, polycrystalline Si film 107 and SiO₂ film 106 in theperipheral circuit region were perfectly eliminated (FIG. 1(e)).

[0055] Next, SiO₂ film 108 was deposited to a thickness of 16 nm by lowpressure chemical vapor deposition (LPCVD) method using SiH4 and N2O assource gases. Deposition temperature was 750° C. Immediately thereafter,SiO₂ film 108 was annealed in an NH3 atmosphere, followed by wetoxidation (FIG. 1(f)).

[0056] Then, a resist pattern was formed by lithography in such a mannerthat the high voltage region alone in the peripheral circuit regionwould be covered (not shown), after which SiO₂ film 108 existing in thelow voltage region alone in the memory cell region and peripheralcircuit region were removed (SiO₂ film 108 becoming 108 a) by a mixedaqueous solution of hydrogen fluoride and ammonia (FIG. 2(a)).

[0057] Thereafter, SiO₂ film 109 was again deposited to a thickness of11 nm by LPCVD using SiH4 and N2O as source gases. Depositiontemperature was 750° C. Immediately thereafter, SiO₂ film 109 wasannealed in an NH3 atmosphere and subjected to wet oxidation (FIG.2(b)).

[0058] Thus, by the steps shown in FIG. 1(f) to FIG. 2(b), there areformed a 11 nm thick interpoly dielectric film (CVD SiO₂ film 109) inthe memory cell region, a 11 nm thick gate oxide film (CVD SiO₂ film109) in the low voltage region of the peripheral circuit region, and anapproximately 27 nm thick gate oxide film (laminate of CVD SiO₂ film 108a and CVD SiO₂ film 109) in the high voltage region of the peripheralcircuit region. Here, the deposited CVD SiO₂ film is annealed in an NH3atmosphere and then subjeted to wet oxidation for the purpose ofreducing the defect in the film called “E′ center” and the hydrogenatoms. This helps to minimize leakage current of the insulating filmswhile reducing trap, thereby improving retention capability of thememory cells. The above operation is also envisaged to improvetransconductance of peripheral circuit MOS transistors.

[0059] Then, phosphorus doped polycrystalline Si film 110 designed toserve as a control gate of each memory cell and gate electrodes ofperipheral circuit was deposited (FIG. 2(c)).

[0060] Thereafter, polycrystalline Si film 110 was patterned bylithography and drying etching to form the control gate (word line) ofeach memory cell and gate electrodes 110 b of peripheral circuit. Afterthis, though not shown in the drawings, SiO₂ film 109 andpolycrystalline Si film 107 a in the memory cell region were etched toform a floating gate (SiO₂ film 109 becomes 109 a and polycrystalline Sifilm 107 a becomes 107 a) (FIG. 2(d)).

[0061] Then, source/drain regions 111 b, 111 c, 112 a, 112 b ofperipheral circuit MOS transistors and those of memory cells (not shown)were formed by ion implantation method (FIG. 2(e)).

[0062] Thereafter, though not shown in the drawings, an intermetalinsulating film was deposited, and in this film contact holes connectingto word line 110 a, gate electrodes 110 b of MOS transistors of theperipheral circuit region and source/drain regions 112, 111 were formed.Then a metal film was deposited and patterned to form electrodes,thereby completing a nonvolatile semiconductor memory device.

[0063]FIG. 3 shows the relation between gate voltage and drain currentof high voltage MOS transistors in the peripheral circuit region formedaccording to the process of the present invention. For the comparison'ssake, there is also shown the result obtained when the gate oxide filmof MOS transistors was formed by thermal oxidation method. In each case,the gate oxide film thickness was 28 nm. In the case of prior art usingthermal oxidation method, a bump called kink was observed in thecurrent/voltage characteristics, indicating characteristic degradationof the device. In contrast, in the case of the present invention usingnitrogen-introduced CVD SiO₂ film, good current/voltage characteristicswere obtained.

[0064]FIG. 4 shows the results of determination of breakdown voltage ofthe gate oxide films of high voltage MOS transistors in the peripheralcircuit region formed by the method of the present invention and theconventional thermal oxidation method. As is seen from FIG. 4, it wasrevealed that breakdown voltage could be increased by usingnitrogen-introduced CVD SiO₂ film as gate oxide film in place of thefilm formed by thermal oxidation.

[0065] For clarifying the difference in characteristics between theprior art and the present invention illustrated in FIGS. 3 and 4, asectional structure of a high voltage MOS transistor according to theprior art and that of the present invention were observed under ascanning transmission electron microscope. Results are shown in FIG. 5.In the case of the prior art using a thermal oxidation film 200 as gateoxide film, the thickness of gate oxide film at the part contiguous tothe shallow groove isolation region indicated by a circle E isremarkably reduced as compared to the central part of the active region(FIG. 5(a)). It was found that this local thinning of the gate oxidefilm was responsible for the degradation of current/voltagecharacteristics or the reduction of breakdown voltage. In contrast, inthe case of the present invention using a nitrogen-introduced CVD SiO₂film, thinning of the gate oxide film near the shallow groove isolationregion, which took place when using the thermal oxidation film, was notinduced (FIG. 5(b)), and this led to the obtainment of goodcharacteristics.

[0066] In application of CVD SiO₂ film to peripheral circuit MOStransistors, nitrogen introduction to such a film is of much account. Inthe production of the nonvolatile semiconductor memory devicesillustrated in FIGS. 1 and 2, in case no annealing was conducted inammonia and also nitrogen was not introduced in forming the CVD SiO₂films 108 and 109, there was seen a notable reduction oftransconductance in MOS transistors in both low voltage and high voltageregions of the peripheral circuit region vis-A-vis the case wherenitrogen was introduced. Breakdown voltage of the gate oxide film alsolowered.

[0067] In Example 1 of the present invention, the interpoly dielectricfilm of memory cells and the gate oxide film of low voltage MOStransistors in the peripheral circuit region are formed by a completelysame step. Therefore, 4 types of gate insulating film including tunneloxide film of memory cell can be actually provided by 3 types of film.This allows a reduction of the number of the production steps over thecase where the gate insulating films are formed independently of eachother.

[0068]FIG. 6 shows the results of determination, by secondary ion massspectroscopy, of nitrogen distribution in the interpoly dielectric filmof memory cell and in the gate oxide films of both low voltage and highvoltage MOS transistors in the peripheral circuit region of thenonvolatile semiconductor memory device produced by the methodillustrated in FIGS. 1 and 2. Although the interpoly dielectric film andthe gate oxide films of low voltage and high voltage MOS transistorswere formed by a same step, the interpoly dielectric film was highest innitrogen concentration, followed by the low voltage region gate oxidefilm and the high voltage region gate oxide film in this order. This canbe accounted for by the fact that the amount of nitrogen introduced intothe SiO₂ film increases with the rise of impurity concentration in thebase Si layer.

[0069] JP-A-11-87545 discloses the techniques for forming the gate oxidefilm of MOS transistors in the peripheral circuit region with a laminateof a tunnel oxide film of memory cell and an interpoly dielectric filmboth of which were formed by CVD. This method, however, had the problemthat since the thickness of gate oxide film of peripheral circuittransistors is decided by the sum of thicknesses of two oxide films ofmemory cell, there is no freedom for the setting of film thickness.Degradation of film characteristics was also a matter of concern withthis method because the tunnel oxide film which incurred damage duringpatterning of the floating gate is used as it is for the gate oxide filmof peripheral circuit transistors. The method according to the instantExample of the present invention has the advantage in that the thicknessof gate oxide film of high voltage MOS transistors in the peripheralcircuit region can be optionally set by properly changing the thicknessof SiO₂ film 108. Further, because of use of wet etching for patterningof SiO₂ film 108, there is no possibility of suffering degradation offilm characteristics due to damage.

[0070] As described above, Example 1 of the present invention has theeffect of improving characteristics and reliability of MOS transistorsin the peripheral circuit region of a nonvolatile semiconductor memorydevice. With regard to such improvement of characteristics andreliability of peripheral circuit MOS transistors, it is not anessential requirement that the whole (low voltage region) or part (highvoltage region) of gate insulating films of peripheral circuit MOStransistors be formed by the same step as the interpoly dielectric filmof memory cell; they may be the insulating films, for example, CVD SiO₂films, formed by deposition. Also, according to the present Example ofthe invention, it is possible to embody a nonvolatile semiconductormemory device production process which enables miniaturizing of thememory cells and lowering of operating voltage. Further, two types ofgate oxide films of peripheral circuit MOS transistors can be madewithout increasing the number of the production steps.

EXAMPLE 2

[0071] This Example concerns another instance of attempt for realizingimprovement of characteristics of peripheral circuit MOS transistors,miniaturizing of memory cells, reduction of operating voltage andsimplification of production process, featuring use ofnitrogen-introduced CVD SiO₂ film for both of the interpoly dielectricfilm of memory cells and gate oxide film of peripheral circuit MOStransistors of a nonvolatile semiconductor memory device andsimultaneously formation of these films.

[0072] The production procedure of the nonvolatile semiconductor memorydevice according to the instant Example is shown in FIGS. 7 to 9, eachof which gives sectional illustrations parallel to the word lines ofmemory cells and perpendicular to the gate lines of peripheral circuitMOS transistors. What is different from Example 1 is that there existsno isolation region separating the cells in the memory cell region, thatthe memory cells are of a so-called virtual ground type in which theadjoining memory cells share the same source and drain, and that eachmemory cell has a third gate 114 a (hereinafter referred to as assistgate) which is different from the floating and control gates. Thisassist gate 114 a is embedded between floating gates 107 b and has afunction to increase the hot electron injection efficiency duringprogramming. It also functions to separate the adjoining memory cells onapplication of 0 V to the gate. This Example, therefore, enables areduction of the memory cell area as compared with the ordinary NOR typecells of Example 1, and is also capable of simultaneous writingoperation with plural cells to improve the programming throughput. It istherefore suited for enlargement of memory density.

[0073] The production process of the nonvolatile semiconductor memorydevice according to this Example is described below.

[0074] First, shallow groove isolation regions 102 separating MOStransistors in the peripheral circuit region were formed on a p-type Sisubstrate with surface orientation (100) (FIG. 7(a)).

[0075] Then, P well regions 104 a, 104 b, 104 c, N well regions 105 a,105 b, and isolation regions 103 separating the wells were formed by ionimplantation method (FIG. 7(b)).

[0076] Next, a SiO₂ film 113, which is to serve as a gate oxide filmbeneath the assist gate, was formed to a thickness of 9 nm by thermaloxidation method (FIG. 7(c)).

[0077] This was followed by 60 nm deposition of a phosphorus-dopedpolycrystalline Si film 114 which serves as an assist gate and 150 nmdeposition of an SiO₂ film 115 (FIG. 7(d)).

[0078] Then, a thick SiO₂ film 115 and a polycrystalline Si film 114were patterned by lithography and dry etching. (SiO₂ film 115 becomes115 a, and polycrystalline Si film 114 becomes 114 a). By thisoperation, SiO₂ film 115 and polycrystalline Si film 114 in theperipheral circuit region were perfectly eliminated (FIG. 7(e)).

[0079] After forming a resist pattern with the memory cell region alonebeing left exposed by lithography (not shown), the source/draindiffusion layer region 116 of memory cell was formed by tilted ionimplantation (FIG. 7(f)).

[0080] After removing gate oxide film 114 remaining in the peripheralcircuit region (not shown), an SiO₂ film 106 which becomes a tunneloxide film of memory cell was formed to a thickness of 9 nm (FIG. 8(e)).

[0081] Then, a phosphorus-doped polycrystalline Si film 107, whichfunctions as a floating gate, was deposited to a thickness of, forexample, 50 nm so that the space between the assist gate patterns wouldnot be filled up (FIG. 8(b)).

[0082] A photoresist 117 was coated so that the space between the assistgate patterns would be perfectly filled up (not shown), and this wasetched back, leaving the space between the assist gate patterns (FIG.8(c)).

[0083] Then, the polycrystalline Si film 107 existing at the part notcovered with photoresist 117 was removed by etch-back. (PolycrystallineSi film 107 becomes 107 a). Etching was controlled so that the depth ofetching would become slightly greater than the thickness ofpolycrystalline Si film 107 (FIG. 8(d)). According to this step, afloating gate pattern having a 3-dimensional shape can be formed by asingle film forming operation.

[0084] Photoresist 117 remaining on polycrystalline Si film 107 a wasremoved by ashing method (FIG. 8(e)).

[0085] Then, SiO₂ film 108 was deposited to a thickness of 16 nm at 750°C. by LPCVD using SiH4 and N2O as source gases. Immediately thereafter,SiO₂ film 108 was annealed in an NH3 atmosphere and subjected to wetoxidation (FIG. 8(f)).

[0086] A resist pattern was formed by lithography so that the highvoltage region alone in the peripheral circuit region would be covered(not shown), and SiO₂ film 108 existing in the memory cell region and inthe low voltage region of the peripheral circuit region was removed by amixed aqueous solution of hydrogen fluoride and ammonia (SiO₂ film 108becomes 108 a) (FIG. 9(a)).

[0087] Then, SiO₂ film 109 was again deposited at 750° C. to a thicknessof 11 nm by LPCVD using SiH4 and N2O as source gases, and immediatelythereafter, SiO₂ film 109 was annealed in an NH3 atmosphere and furthersubjected to wet oxidation (FIG. 9(b)).

[0088] By the steps shown in FIG. 8(f) to FIG. 9(b), there are formedsimilarly to Example 1 a 11 nm thick interpoly dielectric film (CVD SiO₂film 109) in the memory cell region, a 11 nm thick gate oxide film (CVDSiO₂ film 109) in the low voltage region of the peripheral circuitregion, and an approximately 27 nm thick gate oxide film (laminate ofCVD SiO₂ film 108 a and CVD SiO₂ film 109) in the high voltage region ofthe peripheral circuit region.

[0089] Then, a phosphorus-doped polycrystalline Si film 110 designed toserve as a control gate of memory cell and gate electrodes of peripheralcircuit was deposited (FIG. 9(c)).

[0090] This polycrystalline Si film 110 was patterned by a combinationof lithography and dry etching to form control gate (word line) 110 a ofmemory cell and gate electrodes 110 b of peripheral circuit. Then,though not shown in the drawings, SiO₂ film 109 and polycrystalline Sifilm 107 a in the memory cell region were etched to form floating gate(SiO₂ film 109 and polycrystalline Si film 107 a become 109 a and 107 b,respectively) (FIG. 9(d)).

[0091] Then, source/drain regions 111 b, 111 c, 112 a, 112 b ofperipheral circuit MOS transistors were formed (FIG. 9(e)).

[0092] Thereafter, though not shown in the drawings, an intermetalinsulating film was deposited, and in this dielectric film contact holesconnecting to word line 110 a, gate electrodes 110 b of peripheral MOStransistors and source/drain regions 112, 111 were formed. Then a metalfilm was deposited and patterned to form electrodes, thereby completinga nonvolatile semiconductor memory device.

[0093] According to Example 2 described above, as in the case of Example1, improvement was provided to the characteristics and reliability ofperipheral circuit MOS transistors of the nonvolatile semiconductormemory device. It was also possible to realize further miniaturizing ofmemory cells and lowering of operating voltage in comparison withExample 1. Further, two types of gate oxide films of peripheral circuitMOS transistors could be formed without increasing the number of thesteps involved in the production process.

EXAMPLE 3

[0094] Example 3 concerns still another instance of attempt to realizefurther improvement of characteristics of peripheral circuit MOStransistors, miniaturizing of memory cells, lowering of operatingvoltage and simplification of the production process by usingnitrogen-introduced CVD SiO₂ film for the interpoly dielectric films ofboth memory cells and peripheral circuit MOS transistors of thenonvolatile semiconductor memory device and by forming these filmssimultaneously.

[0095] The production procedure of the nonvolatile semiconductor memorydevice according to the instant Example is illustrated in FIGS. 10 to12. The drawings shown are the sectional illustrations parallel to theword lines of memory cells and perpendicular to the gate lines ofperipheral circuit MOS transistors. Example 3 is different from Example1 in that it has a so-called AND structure in which source lines ofmemory cell array are separated and the cells are arranged in parallel.

[0096] The production process is described below.

[0097] First, shallow groove isolation regions 102 separating peripheralcircuit MOS transistors were formed on a p-type Si substrate 101 withsurface orientation (100) (FIG. 10(a)).

[0098] Then, P well regions 104 a, 104 b, 104 c, N well regions 105 a,105 b and well isolation regions 103 were formed by ion implantationmethod (FIG. 10(b)).

[0099] Then, SiO₂ film 106, which is to serve as tunnel oxide film ofeach memory cell, was formed to a thickness of 9 nm by thermal oxidationmethod (FIG. 10(c)).

[0100] Thereafter, phosphorus-doped polycrystalline Si film 118 which isto function as first layer floating gate was deposited to a thickness of100 nm (FIG. 10(d)).

[0101] Then, polycrystalline Si film 118 was patterned by lithographyand dry etching in such a manner that the Si film 118 in the peripheralcircuit region would be left as it was (polycrystalline Si film 118becomes 118 a in the memory cell region and 118 b in the peripheralcircuit region) (FIG. 10(e)).

[0102] Next, source/drain diffusion regions 116 of memory cells wereformed by ion implantation method (FIG. 10(f)).

[0103] SiO₂ film 119 was deposited to a thickness of, for example, 400nm so that the space between the first layer floating gates would beperfectly filled up (FIG. 11(a)).

[0104] SiO₂ film 119 was polished by chemical mechanical polishingmethod (CMP) to expose the first layer floating gate patterns 118 a and118 b (polycrystalline Si films 118 a and 118 b become 118 c and 118 d,respectively) (FIG. 11(b)).

[0105] Then, phosphorus-doped polycrystalline Si film 120 which becomessecond layer floating gate was deposited to a thickness of, for example,50 nm (FIG. 11(c)).

[0106] Then, polycrystalline Si film 120 was patterned by lithographyand dry etching (polycrystalline Si film 120 becomes 120 a). By thisoperation, polycrystalline Si film 120 in the peripheral circuit regionand polycrystalline Si film 118 d existing thereunder were perfectlyremoved (FIG. 11(d)). In the memory cells of the nonvolatilesemiconductor device according to the present Example, polycrystallineSi films 118 c and 120 a are electrically connected, and floating gateis formed by these two films.

[0107] Then, SiO₂ film was deposited at 750° C. to a thickness of 16 nmby LPCVD using SiH4 and N2O as source gases, and immediately thereafter,SiO₂ film 108 was annealed in an NH3 atmosphere and subjected to wetoxidation (FIG. 11(e)).

[0108] Next, resist pattern was formed by lithography covering the highvoltage region alone in the peripheral circuit region (not shown), andSiO₂ film 108 existing in the memory cell region and the peripheralcircuit low voltage region was removed by a mixed aqueous solution ofhydrogen fluoride and ammonia (SiO₂ film 108 becomes 108 a) (FIG.12(a)).

[0109] Then, SiO₂ film 109 was again deposited at 750° C. to a thicknessof 11 nm by LPCVD using SiH4 and N2O as acting gases, and immediatelythereafter, SiO₂ film 109 was annealed in an NH3 atmosphere and furthersubjected to wet oxidation (FIG. 12(b)).

[0110] Thus, by the steps shown in FIGS. 11(e) to 12(b), there areformed a 11 nm thick interpoly dielectric film (CVD SiO₂ film 109) inthe memory cell region, a 11 nm thick gate oxide film (CVD SiO₂ film109) in the peripheral circuit low voltage region, and an approximately27 nm thick gate oxide film (laminate of CVD SiO₂ film 108 a and CVDSiO₂ film 109) in the peripheral circuit high voltage region, as inExample 1.

[0111] Then, phosphorus-doped polycrystalline Si films 110 which aredesigned to become control gates of memory cells and gate electrodes ofperipheral circuit region MOS transistors (FIG. 11(c)).

[0112] Thereafter, polycrystalline Si film 110 was patterned bylithography and dry etching to form control gate (word line) of memorycell and gate electrodes 110 b of peripheral circuit. Then, though notshown, SiO₂ film 109 and polycrystalline Si films 120 a, 118 c in thememory cell region were etched to form floating gates (SiO₂ film 109becomes 109 a and polycrystalline Si films 120 a and 118 c become 120 band 118 d, respectively) (FIG. 11(d)).

[0113] Then, source/drain regions 111 b, 111 c, 112 a, 112 b ofperipheral circuit MOS transistors were formed (FIG. 11(e)).

[0114] Next, though not shown, an intermetal insulating film wasdeposited, and in this film contact holes connecting to word line 110 a,gate electrodes 110 b of peripheral circuit MOS transistors, andsource/drain regions 112, 111 were formed, and then a metal film wasdeposited and patterned to form electrodes, thereby completing anonvolatile semiconductor memory device.

[0115] According to Example 3 described above, like in Example 1, thecharacteristics and reliability of peripheral circuit MOS transistors ofnonvolatile semiconductor memory device were improved. It was alsopossible to realize miniaturizing of the memory cells and lowering ofoperating voltage. Further, the two types of gate oxide films ofperipheral circuit MOS transistors could be formed without increasingthe number of the steps in the production process.

EXAMPLE 4

[0116] This Example concerns an embodiment in which a thin thermal oxidefilm is used in place of the nitrogen-introduced CVD SiO₂ film as partof the gate oxide films of MOS transistors in the peripheral circuithigh voltage region.

[0117] The producing procedure of the nonvolatile semiconductor memorydevice of this Example is shown in FIG. 13. The steps until formation offloating gates 107 a in the production procedure of this nonvolatilesemiconductor device are the same as shown in FIGS. 1(a) to 1(e) ofExample 1, so the explanation of these steps is not given here.

[0118] After forming the floating gate patterns such as shown in FIG.1(e), SiO₂ film 121 was deposited to a thickness of 4 nm by LPCVD usingSiH4 and N2O as source gases (FIG. 13(a)).

[0119] Then, Si3N4 film 122 was deposited to a thickness of 10 nm byLPCVD, after which resist pattern was formed by lithography in such amanner that the high voltage region alone of the peripheral circuitregion would be exposed (not shown), and Si3N4 film 122 existing in thehigh voltage region was removed by dry etching (FIG. 13(b)).

[0120] After removing SiO₂ film 121 existing in the high voltage regionwith an aqueous hydrogen fluoride solution (not shown), SiO₂ film 123was selectively grown only in the peripheral circuit high voltage regionnot covered with Si3N4 film 122 by thermal oxidation method. The formedoxide film thickness was 16 nm. Since said Si3N4 film 122 has oxidationresistance, the oxidation reaction does not proceed in the memory cellregion and in the peripheral circuit low voltage region which arecovered with Si3N4 film 122 (FIG. 13(c)).

[0121] After eliminating Si3N4 film 122 with a hot phosphoric acidaqueous solution, SiO₂ film 121 existing in the memory cell region andin the peripheral circuit low voltage region was removed with an aqueoushydrogen fluoride solution. In this operation, SiO₂ film 123 of theperipheral circuit high voltage region is also slightly etched at itssurface, with its thickness being reduced to 14 nm (SiO₂ film 123becomes 123 a) (FIG. 13(d)).

[0122] Then, SiO₂ film 109 was deposited at 750° C. to a thickness of 11nm by LPCVD using SiH4 and N2O as source gases, and immediatelythereafter, SiO₂ film 109 was annealed in an NH3 atmosphere and furthersubjected to wet oxidation (FIG. 13(e)).

[0123] By the above steps, there were formed a 11 nm thick interpolydielectric film (CVD SiO₂ film 109) in the memory cell region, a 11 nmthick gate oxide film (CVD SiO₂ film 109) in the peripheral circuit lowvoltage region, and an approximately 25 nm thick gate oxide film(laminate of thermal oxidation SiO₂ film 123 a and CVD SiO₂ film 109) inthe peripheral circuit high voltage region.

[0124] Thereafter, the steps of FIGS. 2(c) to 2(e) of Example 1 wereconducted to complete a nonvolatile semiconductor memory device.

[0125] In Example 4, it was possible to make a nonvolatile semiconductormemory device with the same number of masks as needed in Example 1 byusing the thermal oxidation method. Also, the gate oxide film/Sisubstrate interfacial characteristics of MOS transistors in theperipheral circuit high voltage region were improved and the conductanceenhanced in comparison with Example 1.

[0126] In Example 4, the gate oxide film of MOS transistors in theperipheral circuit high voltage region is constituted by a thermaloxidation film and a nitrogen-introduced CVD SiO₂ film. Due to thermaloxidation, there was observed a slight decrease of gate oxide filmthickness, such as shown in FIG. 5(a), at the part contiguous to theshallow groove isolation region. However, since the oxide film thicknesswas small (14 nm) as compared to the prior art film, the degradation ofcurrent-voltage characteristics and breakdown voltage of MOS transistorswas limited to a level that posed no practical problem.

EXAMPLE 5

[0127] As stated in Example 4, even when thermal oxidation film is usedas gate oxide film of peripheral circuit MOS transistors, the degree ofthinning of the oxide film at the part contiguous to the shallow grooveisolation region is small and the degradation of MOS characteristics canbe restricted to a level that presents no practical problem if the oxidefilm thickness is small. So, in this Example is described the instancewhere the thinned thermal oxidation film was used as gate oxide film oflow voltage MOS transistors in the peripheral circuit region to improveperformance of the nonvolatile semiconductor memory device.

[0128] The production procedure of the nonvolatile semiconductor memorydevice according to the instant Example is illustrated in FIGS. 14 to15. Since the steps until formation of the well regions are the same asthose of Example 1 illustrated in FIGS. 1(a) to 1(b), they are notexplained here.

[0129] After forming the isolation regions and the well regions asillustrated in FIGS. 1(a) to 1(b) of Example 1, SiO₂ film which becomestunnel dielectric film of memory cells was formed by thermal oxidationmethod (FIG. 14(a)).

[0130] Then, a resist pattern designed to leave the low voltage regionalone in the peripheral circuit region exposed was formed by lithography(not shown), and SiO₂ film 106 in the low voltage region was removed bya mixed aqueous solution of hydrogen fluoride and ammonia (FIG. 14(b)).

[0131] Then, SiO₂ film 124 which becomes gate oxide film of MOStransistors in the peripheral circuit low voltage region was formed to athickness of 5 nm by thermal oxidation method (FIG. 14(c)).

[0132] Then, phosphorus-doped polycrystalline Si film 107 which becomesfloating gate was deposited to a thickness of 150 nm (FIG. 14(d)).

[0133] Thereafter, polycrystalline Si film 107 was patterned bylithography and dry etching. In this operation, polycrystalline Si film107 in the peripheral circuit region was perfectly removed in the highvoltage region, but was left so that it would be entirely covered in thelow voltage region (polycrystalline Si film 107 becomes 107 a and 107 c)(FIG. 14(e)).

[0134] Next, SiO₂ film 108 was deposited at 750° C. to a thickness of 16nm by LPCVD using SiH4 and N2O as source gases, and immediatelythereafter, SiO₂ film 108 was annealed in an NH3 atmosphere andsubjected to wet oxidation (FIG. 14(f)).

[0135] Then, a resist pattern was formed by lithography covering SiO₂film 108 in the high voltage region alone of the peripheral circuitregion (not shown), and SiO₂ film 108 present in the memory cell regionand in the peripheral circuit low voltage region was removed by a mixedaqueous solution of hydrogen fluoride and ammonia (SiO₂ film 108 becomes108 a) (FIG. 15(a)).

[0136] Then, SiO₂ film 109 was again deposited at 750° C. to a thicknessof 11 nm by LPCVD using SiH4 and N2O as source gases, immediatelyfollowed by annealing of SiO₂ film 109 in an NH3 atmosphere and wetoxidation (FIG. 15(b).

[0137] By the above steps, there are formed a 11 nm thick interpolydielectric film (CVD SiO₂ film 109) in the memory cell region, a 5 nmthick gate oxide film (thermally oxidized SiO₂ film 124) in theperipheral circuit low voltage region, and an approximately 27 nm thickgate oxide film (laminate of CVD SiO₂ film 108 a and CVD SiO₂ film 109)in the peripheral circuit high voltage region.

[0138] Then, phosphorus-doped polycrystalline Si film 110 which formsmemory cell control gates and peripheral circuit gate electrodes wasdeposited (FIG. 15(c)).

[0139] Then, polycrystalline Si film 110 was patterned by lithographyand dry etching to form memory cell control gate (word line) 110 a andperipheral circuit gate electrodes 110 b. Thereafter, though not shown,SiO₂ film 109 and polycrystalline Si films 107 a, 107 c of the memorycell region and of MOS transistors in the peripheral circuit low voltageregion are etched, thereby completing the floating gates (SiO₂ film 109becomes 109 a and polycrystalline Si films 107 a and 107 c become 107 band 107 d, respectively). Here, patterning was conducted so that part ofpolycrystalline Si films 107 d in the peripheral circuit low voltageregion would be exposed (FIG. 15(d)).

[0140] Next, source/drain regions 111 b, 111 c, 112 a, 112 b of memorycells and peripheral circuit MOS transistors (source/drain regions ofmemory cells being not shown) were formed by ion implantation method,after which, though not shown, an intermetal insulating film wasdeposited, and in this film contact holes connecting to word line 110 a,gate electrodes 110 b of peripheral circuit MOS transistors andsource/drain regions 112, 111 were formed. Then, a metal film wasdeposited and patterned to form electrodes. In this operation, contactholes and metal electrodes are so disposed that polycrystalline Si films110 b and 107 d would be electrically connected to each other in theperipheral circuit low voltage region. By this arrangement, in the MOStransistors in the peripheral circuit low voltage region, the voltageapplied to polycrystalline Si film 110 b is also applied to 107 d. Bycarrying out the above process, a nonvolatile semiconductor memorydevice was completed (FIG. 15(e)).

[0141] The nonvolatile semiconductor memory device produced according toExample 5, like that of Example 1, was improved in characteristics andreliability of peripheral circuit MOS transistors. It was also possibleto realize miniaturizing of memory cells and a reduction of operatingvoltage. Further, gate oxide films of peripheral circuit MOS transistorscould be reduced to two types without increasing the number of thesteps. Moreover, as compared to Example 1, high-speed operation of theperipheral circuit low voltage region was made possible, andprogramming/erasing and reading speed was improved.

EXAMPLE 6

[0142] Described here is still another instance of attempt to improveperformance of nonvolatile semiconductor memory device by using alaminate of a thinned thermal oxide film and a nitrogen-introduced CVDSiO₂ film as gate oxide film of MOS transistors in the high voltageregion of the peripheral circuit region.

[0143] The production procedure of the nonvolatile semiconductor memorydevice of Example 6 is illustrated in FIGS. 16 to 17. The steps untilformation of the well regions are the same as those illustrated in FIGS.1(a) to 1(b) of Example 1 and therefore need not be explained here.

[0144] After forming the isolation regions and the well regions asillustrated in FIGS. 1(a) to 1(b) of Example 1, SiO₂ film 125 wasdeposited at 750° C. to a thickness of 20 nm by LPCVD using SiH4 and N₂Oas source gases, and immediately thereafter, SiO₂ film 108 was annealedin an NH3 atmosphere and further subjected to wet oxidation (FIG.16(a)).

[0145] Then, a resist pattern designed to cover the high voltage sectionalone of the peripheral circuit region was formed by lithography (notshown), and SiO₂ film 125 in the memory cell region and the low voltageregion of the peripheral circuit region was removed by a mixed aqueoussolution of hydrogen fluoride and ammonia (SiO₂ film 125 becomes 125 a)(FIG. 16(b)).

[0146] Next, SiO₂ film 126 designed to constitute tunnel dielectric filmand gate oxide film in the peripheral circuit low voltage region wasformed to a thickness of 9 nm by thermal oxidation method. In thisoperation, oxide film 126 a grows in the peripheral circuit high voltageregion, too, although its growth is not equal to that in the memory cellregion.

[0147] By the above steps, there are formed a 9 nm tunnel dielectricfilm (thermal oxidation SiO₂ film 126) in the memory cell region, a 9 nmgate oxide film (thermal oxidation SiO₂ film 126) in the peripheralcircuit low voltage region, and a roughly 27 nm gate oxide film(laminate of thermal oxidation SiO₂ film 126 a and CVD SiO₂ film 125 a)in the peripheral circuit high voltage region (FIG. 16(c)).

[0148] Then, phosphorus-doped polycrystalline Si film 107, which becomesfloating gate, was deposited to a thickness of 150 nm (FIG. 16(d)).

[0149] Thereafter, polycrystalline Si film 107 was patterned bylithography and dry etching. In this operation, polycrystalline Si film107 in the peripheral circuit region was left in such a way that itwould be entirely covered (polycrystalline Si film 107 becomes 107 a inthe memory cell region and 107 e in the peripheral circuit region) (FIG.16(e)).

[0150] Then, SiO₂ film 109, which is to serve as interpoly dielectricfilm, was deposited at 750° C. to a thickness of 11 nm by LPCVD usingSiH4 and N2O as source gases, and immediately thereafter, SiO₂ film 109was annealed in an NH3 atmosphere and further subjected to wet oxidation(FIG. 17(a)).

[0151] Next, phosphorus-doped polycrystalline Si film 110, which is toform memory cell control gates and peripheral circuit gate electrodes,was deposited (FIG. 17(b)).

[0152] Thereafter, polycrystalline Si film 110 was patterned bylithography and dry etching to form memory cell control gates (wordlines) 110 a and peripheral circuit gate electrodes 110 b, and then,though not shown, SiO₂ film 109 and polycrystalline Si films 107 a, 107e in the memory cell region and of MOS transistors in peripheral circuitregion were etched, thereby completing the floating gates (SiO₂ film 109becomes 109 a and polycrystalline Si films 107 a and 107 c become 107 band 107 f, respectively). Patterning was conducted so that part ofpolycrystalline Si films 107 d in the peripheral circuit region would beexposed (FIG. 17(c)).

[0153] Next, source/drain regions 111 b, 111 c, 112 a, 112 b of memorycells and peripheral circuit region MOS transistors (source/drainregions of memory cells being not shown) were formed by ion implantationmethod. Then, though not shown, an intermetal insulating film wasdeposited, and in this intermetal insulating film contact holesconnecting to word lines 110 a, gate electrodes 110 b of peripheralcircuit region MOS transistors, and source/drain regions 112, 111 wereformed. Then a metal film was deposited and patterned to formelectrodes. In this operation, in the peripheral circuit region, contactholes and metal electrodes were so disposed that polycrystalline Sifilms 110 b and 107 d would be electrically connected. By thisarrangement, in MOS transistors in the peripheral circuit region, thevoltage applied to polycrystalline Si film 110 b is also applied topolycrystalline Si film 107 d. By the above process, a nonvolatilesemiconductor memory device was completed (FIG. 17(d)).

[0154] The nonvolatile semiconductor memory device of this Example, likethat of Example 1, was improved in characteristics and reliability ofMOS transistors in the peripheral circuit region. It was also possibleto realize miniaturization of memory cells and lowering of operatingvoltage. Further, two types of gate oxide films of peripheral circuitMOS transistors could be formed without increasing the number of thesteps. Still further, high-speed operation of peripheral circuit lowvoltage region was made possible and programming/erasing and readingspeed was enhanced in comparison with Example 1.

[0155] In the above Examples, the invention has been describedconcerning its embodiments using NOR type, assist gate type and AND typememory cells, but the similar effect can be obtained by using othertypes of memory cells, such as NAND type, split gate type and erase gatetype.

[0156] The same effect can also be obtained when the invention isapplied to a product in which nonvolatile semiconductor memory deviceand microcontroller are embedded in a single chip.

[0157] (Effect of the Invention)

[0158] According to the present invention, reliability of gate oxidefilms of peripheral circuit region MOS transistors and transistorcharacteristics of nonvolatile semiconductor memory device are improved.It is also possible to realize miniaturizing of the nonvolatilesemiconductor memory device and lowering of its operating voltage.Further, the production process of this nonvolatile semiconductor memorydevice can be simplified.

What is claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a memory cell region composed of a memory cell arraycomprising a plurality of memory cells arranged as a matrix, each ofsaid memory cells comprising first MOS field effect transistors eachhaving a first well region formed in a semiconductor substrate, a firstdiffusion layer formed in said first well region and designed tofunction as source and drain, a floating gate formed on said well withthe interposition of a tunnel dielectric film, and a control gate formedabove said floating gate with the interposition of an interpolydielectric film, and a peripheral circuit region having disposed thereina plurality of second MOS field effect transistors, each unitarytransistor having a second well region formed in a semiconductorsubstrate, a second diffusion layer formed in said second well anddesigned to function as source and drain, and gate electrodes formed onsaid second well with the interposition of a gate insulating film,wherein isolation between said plurality of second MOS field effecttransistors is effected by shallow groove isolation method, and at leastone of said gate insulating films of said plurality of second MOS fieldeffect transistors comprises a first insulating film deposited on thesemiconductor substrate.
 2. The memory device according to claim 1wherein the first insulating film is a silicon oxide film.
 3. The memorydevice according to claim 2 wherein nitrogen is introduced into thesilicon oxide film.
 4. The memory device according to claim 1 whereinthe interpoly dielectric film comprises a second deposited insulatingfilm which is substantially equal to said first insulating film inthickness.
 5. The memory device according to claim 4 wherein said firstand second insulating films are a silicon oxide film.
 6. The memorydevice according to claim 5 wherein nitrogen is introduced into saidsilicon oxide film.
 7. The memory device according to claim 6 whereinthe nitrogen concentration in said second insulating film is higher thanthat in the first insulating film.
 8. A nonvolatile semiconductor memorydevice comprising: a memory cell region composed of a memory cell arraycomprising a plurality of memory cells arranged as a matrix, each ofsaid memory cells comprising first MOS field effect transistors eachhaving a first well region formed in a semiconductor substrate, a firstdiffusion layer formed in said first well region and designed tofunction as source and drain, a floating gate formed on said well withthe interposition of a tunnel dielectric film, and a control gate formedabove said well with the interposition of an interpoly dielectric film,and a peripheral circuit region provided with second MOS field effecttransistors each having a second well region formed in the semiconductorsubstrate, a second diffusion layer formed in said second well regionand designed to function as source and drain, and first gate electrodesformed on said second well with the interposition of a first gateinsulating film, and third MOS field effect transistors each having athird well region formed in the semiconductor substrate, a thirddiffusion layer formed in said third well region and designed tofunction as source and drain, and second gate electrodes formed on saidthird well with the interposition of a second insulating film which isgreater than said first gate insulating film in thickness, whereinisolation in said peripheral circuit region is effected by shallowgroove isolation method, and said second gate insulating film comprisesa first insulating film deposited on the semiconductor substrate.
 9. Thememory device according to claim 8 wherein the first insulating film isa silicon oxide film.
 10. The memory device according to claim 9 whereinnitrogen is introduced into the silicon oxide film.
 11. The memorydevice according to claim 8 wherein each of the interpoly dielectricfilm and the first gate insulating film comprises a second depositedinsulating film.
 12. The memory device according to claim 11 whereinboth of the first and second insulating film are a silicon oxide film.13. The memory device according to claim 12 wherein nitrogen isintroduced into the silicon oxide film.
 14. The memory device accordingto claim 13 wherein the nitrogen concentration in the films is higher inthe order of interpoly dielectric film, first gate insulating film andsecond gate insulating film.
 15. A nonvolatile semiconductor memorydevice comprising: a memory cell region composed of a memory cell arraycomprising a plurality of memory cells arranged as a matrix, each memorycell comprising first MOS field effect transistors each having a firstwell region formed in a semiconductor substrate, a first diffusion layerformed in said first well region and designed to function as source anddrain, a floating gate formed on said well with the interposition of atunnel dielectric film, and a control gate formed above said floatinggate with the interposition of an interpoly dielectric film, and aperipheral circuit region having disposed therein a plurality of secondMOS field effect transistors, each unitary transistor having a secondwell region formed in the semiconductor substrate, a second diffusionlayer formed in said well region and designed to function as source anddrain, and gate electrodes formed on said second well with theinterposition of a gate insulating film, wherein isolation between saidplurality of second MOS field effect transistors is effected by shallowgroove isolation method, and at least one of said gate insulating filmsof said plurality of second MOS field effect transistors comprises afirst insulating film formed by thermally oxidizing the semiconductorsubstrate and a second insulating film deposited on said firstinsulating film.
 16. The memory device according to claim 15 wherein thefirst insulating film is smaller than the second insulating film inthickness.
 17. The memory device according to claim 15 wherein thesecond insulating film is a silicon oxide film.
 18. The memory deviceaccording to claim 17 wherein nitrogen is introduced into the siliconoxide film.
 19. The memory device according to claim 15 wherein theinterpoly dielectric film comprises a third deposited insulating filmwhich is substantially equal to the second insulating film in thickness.20. The memory device according to claim 19 wherein the secondinsulating film and the third insulating film are each a silicon oxidefilm.
 21. The memory device according to claim 20 wherein nitrogen isintroduced into the silicon oxide film.
 22. The memory device accordingto claim 21 wherein the nitrogen concentration in the third insulatingfilm is higher than that in the second insulating film.
 23. Anonvolatile semiconductor memory device comprising: a memory cell regioncomposed of a memory cell array comprising a plurality of memory cellsarranged as a matrix, each memory cell comprising first MOS field effecttransistors each having a first well region formed in a semiconductorsubstrate, a first diffusion layer formed in said first well region anddesigned to function as source and drain, a floating gate formed on saidwell with the interposition of a tunnel dielectric film, and a controlgate formed above said floating gate with the interposition of aninterpoly dielectric film, and a peripheral circuit region provided withsecond MOS field effect transistors each having a second well regionformed in the semiconductor substrate, a second diffusion layer formedin said second well region and designed to function as source and drain,and first gate electrodes formed on said second well with theinterposition of a first insulating film, and third MOS field effecttransistors each having a third well region formed in the semiconductorsubstrate, a third diffusion layer formed in said third well region anddesigned to function as source and drain, and second gate electrodesformed on said third well with the interposition of a second insulatingfilm which is greater than said first gate insulating film in thickness,wherein isolation in said peripheral circuit region is effected byshallow groove isolation method, and the second insulating filmcomprises a first insulating film formed by thermally oxidizing thesemiconductor substrate and a second insulating film deposited on saidfirst insulating film.
 24. The memory device according to claim 23wherein the second insulating film is a silicon oxide film.
 25. Thememory device according to claim 24 wherein nitrogen is introduced intothe silicon oxide film.
 26. The memory device according to claim 23wherein the interpoly dielectric film and the first gate insulating filmcomprise a third deposited insulating film which is substantially equalto the second insulating film in thickness.
 27. The memory deviceaccording to claim 26 wherein the second insulating film and the thirdinsulating film are both a silicon oxide film.
 28. The memory deviceaccording to claim 27 wherein nitrogen is introduced into the siliconoxide film.
 29. The memory device according to claim 28 wherein thenitrogen concentration in the films is higher in the order of interpolydielectric film, first gate insulating film and second gate insulatingfilm.
 30. The memory device according to claim 23 wherein the interpolydielectric film comprises a third deposited insulating film which issubstantially equal to the second insulating film in thickness.
 31. Thememory device according to claim 30 wherein the second insulating filmand the third insulating film are a silicon oxide film.
 32. The memorydevice according to claim 31 wherein nitrogen is introduced into thesilicon oxide film.
 33. The memory device according to claim 32 whereinthe nitrogen concentration in the interpoly dielectric film is higherthan that in the second gate insulating film.
 34. A process forproducing a nonvolatile semiconductor memory device comprising aplurality of memory cells each having a floating gate formed on asemiconductor substrate with the interposition of a tunnel dielectricfilm and a control gate formed on said floating gate with theinterposition of an interpoly dielectric film, and a plurality of fieldeffect transistors each having gate electrodes formed on thesemiconductor substrate with the interposition of a gate insulatingfilm, said process comprising the steps of: forming a shallow grooveisolation region on a semiconductor substrate; forming a tunneldielectric film on the semiconductor substrate surface in said memorycell formed region by thermal oxidation method, depositing a firstpolycrystalline Si film which becomes said floating gate, and thenremoving the first polycrystalline Si film in said field effecttransistor formed region; depositing a first silicon oxide film whichbecomes the first portion of said gate insulating film, and thenremoving the first silicon oxide film in said memory cell formed region;depositing a second silicon oxide film which becomes said interpolydielectric film and a second portion of said gate insulating film; anddepositing a second polycrystalline Si film which becomes said controlgate and said gate electrodes.
 35. The process according to claim 34wherein in the fourth and fifth steps, the first and second siliconoxide films just after deposition are annealed in an NH3 atmosphere andfurther subjected to wet oxidation.
 36. The process according to claim34 wherein in the third and sixth steps, the first and secondpolycrystalline Si films are doped with phosphorus.
 37. A process forproducing a nonvolatile semiconductor memory device comprising aplurality of memory cells each having a floating gate formed on asemiconductor substrate with the interposition of a tunnel dielectricfilm and a control gate formed on said floating gate with theinterposition of an interpoly dielectric film, and a plurality of fieldeffect transistors each having gate electrodes formed on thesemiconductor substrate with the interposition of a gate insulatingfilm, said process comprising the steps of: forming a shallow grooveisolation region on the semiconductor substrate; forming a tunneldielectric film on the semiconductor substrate surface in the memorycell formed region by thermal oxidation method; depositing a firstpolycrystalline Si film which becomes said floating gate, and thenremoving the first polycrystalline Si film in said field effecttransistor formed region; forming a first silicon oxide film, whichbecomes a first portion of said gate insulating film, on thesemiconductor substrate surface in the field effect transistor formedregion by thermal oxidation method; depositing a second silicon oxidefilm which becomes said interpoly dielectric film and a second portionof said gate insulating film; and depositing a second polycrystalline Sifilm which becomes said control gate and said gate electrodes.
 38. Theprocess according to claim 37 wherein in the fifth step, the secondsilicon oxide film just after its deposition is annealed in an NH₃atmosphere and further subjected to wet oxidation.
 39. The processaccording to claim 37 wherein in the third and sixth steps, the firstand second polycrystalline Si films are doped with phosphorus.
 40. Aprocess for producing a nonvolatile semiconductor memory devicecomprising a plurality of memory cells each having a floating gateformed on a semiconductor substrate with the interposition of a tunneldielectric film and a control gate formed on said floating gate with theinterposition of an interpoly dielectric film, and a plurality of fieldeffect transistors each having gate electrodes formed on thesemiconductor substrate with the interposition of a gate insulatingfilm, said process comprising the steps of: forming a shallow grooveisolation region on a semiconductor substrate; depositing a firstsilicon oxide film which becomes a first portion of said gate insulatingfilm, and then removing said first silicon oxide film in the memory cellformed region; forming a tunnel dielectric film on the semiconductorsubstrate surface in the memory cell formed region and forming a secondsilicon oxide film which becomes a second portion of said gateinsulating film between said semiconductor substrate in the transistorformed region and said first silicon oxide film, both by thermaloxidation method; depositing a first polycrystalline Si film whichbecomes said floating gate and said gate electrodes; depositing a thirdsilicon oxide film which becomes said interpoly dielectric film; anddepositing a second polycrystalline Si film which becomes said controlgate.
 41. The process according to claim 40 wherein in the second andfifth steps, the first and third silicon oxide films immediately aftertheir deposition are annealed in an NH₃ atmosphere and further subjectedto wet oxidation.
 42. The process according to claim 40 wherein in thefourth and sixth steps, the first and second polycrystalline Si filmsare doped with phosphorus.